The invention relates to a semiconductor device having a MIM (Metal-Insulator-Metal) structure.
In a high-frequency analog integrated circuit used in the field of mobile communications etc, in addition to active elements (transistor elements (devices) etc) operating at a high speed, passive elements such as resistance (resistor), capacitance (capacitor) and an inductor are required. Then, these circuits are required to reduce parasitic resistance and parasitic capacitance in order to improve the operating speed and to decrease power consumption. In these elements, the capacitance element involves using a MIM (Metal-Insulator-Metal) element capable of reducing greater quantities of the parasitic resistance and of the parasitic capacitance than by a conventional MOS type capacitance element (e.g., Patent document 1 given below).
Further, in terms of reducing the parasitic capacitance and attaining the high-speed operation of the element (device), it is examined that a metal wiring of copper (Cu) etc is applied to the integrated circuit (refer to Patent document 2 given below).    [Patent document 1] Japanese Patent Application Laid-Open Publication No. 2001-237375    [Patent document 2] Japanese Patent Application Laid-Open Publication No. 2003-264235    [Patent document 3] Japanese Patent Application Laid-Open Publication No. 2004-63990